CPU Microarchitecture & RTL Design Engineer

Quick Facts

• Role: CPU Microarchitecture & RTL Design Engineer

• Focus: CPU microarchitecture development, RTL ownership, validation, and performance exploration

Description

Own or contribute to microarchitecture development and specification from early exploration through detailed definition, then drive RTL development, assessment, and refinement to hit power, performance, area, and timing targets. Support validation through testbench development and simulation, and perform performance exploration and correlation to ensure the RTL meets goals. Collaborate with cross-functional engineering teams to implement and validate design aspects including timing, area, reliability, testability, and power, while leading CPU RTL efforts across core areas.

Responsibilities

• Microarchitecture development and specification (architectural exploration → detailed specification)

• RTL ownership (development, assessment, refinement for power/performance/area/timing)

• Validation support (testbench development, functional and performance verification)

• Performance exploration and correlation (high-performance strategy validation)

• Design delivery collaboration (timing, area, reliability, testability, power)

Requirements

• BS degree

• 15+ years of relevant industry experience

• Technical leadership of senior engineers delivering complex microarchitecture definition and RTL development

• Mentoring and supporting technical development of other engineers

• Deep expertise in one or more CPU microprocessor architecture areas (e.g., instruction fetch/decode, branch prediction, scheduling/register renaming, out-of-order execution, execution units, load/store, cache/memory subsystems)

• Low power microarchitecture understanding

• High performance microarchitecture trade-off knowledge

• Experience applying GenAI to accelerate CPU performance/power/area improvements while maintaining schedule and quality

• C or C++ programming experience

• Interpretive language experience such as Perl or Python

• Knowledge of microprocessor architecture

• Verilog and/or VHDL knowledge

• Experience with simulators and waveform debugging tools

• Understanding of logic design principles plus timing and power implications

Benefits

• Lead and deliver groundbreaking CPU microarchitecture and RTL work with a focus on high performance and low power

• Work with cross-functional teams to validate power/performance/area/timing and broader physical design aspects