RTL Design Engineer (Networking / NoC)

Quick Facts

• Role: RTL Design Engineer (Networking / NoC)

• Focus: Next-generation AI accelerator silicon RTL, with emphasis on interconnect networking and NoC

Description

You will work on next-generation AI accelerator silicon by translating system-level and performance requirements into efficient, scalable hardware microarchitectures. This is a hands-on RTL design role focused on high-performance datapaths, control logic, and interconnect/networking subsystems, with a strong interest in Network-on-Chip (NoC). You’ll collaborate across architecture, software, verification, and physical design teams and help drive hardware/software co-design for performance, power, area, and scalability.

Responsibilities

• Design and implement high-performance RTL from microarchitecture definition through implementation and integration

• Translate system-level requirements into hardware microarchitectures with architecture and software teams

• Drive hardware/software co-design to optimize performance, power, area, and scalability for AI workloads

• Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems

• Evaluate architectural tradeoffs across bandwidth, latency, throughput, and resource utilization

• Partner with design verification and formal verification teams to ensure functional correctness and debug issues

• Work with physical design teams to optimize RTL for synthesis, timing closure, power, and area

• Contribute to architecture reviews and design specifications

• Support block-level and SoC-level integration, debugging, and performance optimization

Requirements

• Strong hands-on ASIC RTL design and microarchitecture development experience using SystemVerilog or Verilog

• Experience designing and implementing complex digital hardware blocks end-to-end (architecture/specification → RTL development → verification)

• Understanding of hardware architecture and microarchitecture tradeoffs (performance, power, area, latency, throughput)

• Experience collaborating across architecture, software, verification, and physical design teams

• Ability to identify performance bottlenecks and translate architectural requirements into efficient RTL implementations

• Experience with synthesis, timing closure, and physical implementation considerations

• Comfort working on ambiguous, technically challenging problems and owning designs from concept through integration

• Experience with Network-on-Chip (NoC), networking, interconnect fabrics, packet-based architectures, or high-bandwidth data movement (preferred)

Benefits

• Opportunity to influence architectural decisions and drive microarchitecture development

• Own RTL design from early concept through implementation and integration

• Work on challenging, high-impact AI accelerator hardware in a cross-functional engineering environment