Front-End Design Engineer

Quick Facts

• Role: Front-End Design Engineer (40 hours/week)
• Focus: RTL synthesis, verification, optimization, and timing/robustness checks

Description

Convert RTL designs into netlists using industry-standard RTL synthesis tools. Optimize power, performance, and area by experimenting with synthesis recipes and improving existing synthesis methodologies. Work with Verilog and SystemVerilog RTL to correlate code with gate-level circuits and guide optimal RTL solutions.

Responsibilities

• Convert RTL designs into netlists using RTL synthesis tools
• Optimize PPA through synthesis recipe experimentation and methodology improvements
• Understand Verilog/SystemVerilog RTL and relate it to gate-level circuits to develop improved RTL
• Perform Clock and Reset Domain Crossing (CDC/RDC) checks
• Run lint checks for RTL quality
• Perform logical equivalence checks to ensure netlist correctness and support ECO generation
• Conduct static timing analysis (STA), identify critical paths, and propose solutions across physical implementation and microarchitectural optimizations
• Analyze RTL simulation waveforms using industry-standard simulators to understand design intent and signal activity
• Collaborate with internal R&D teams

Requirements

• Master’s degree (or foreign equivalent) in Electrical and Computer Engineering, Electrical Engineering, or related field
• 1 year of experience in the job offered or a related occupation
• Synthesizing RTL designs into netlists using Design Compiler/Genus
• Understanding RTL and making RTL updates for PPA
• Creating unit testbenches to verify RTL updates
• Working with simulation waveforms to understand design intent
• Performing Static Timing Analysis (STA) and achieving timing closure
• Performing lint checks to ensure RTL quality
• Performing Clock Domain Crossing (CDC) checks
• Performing Reset Domain Crossing (RDC) checks

Benefits

Not specified in the provided posting.