FPGA Design Engineer

Quick Facts

• Role: FPGA Design Engineer

Description

Design and implement RTL at the block and subsystem level for cryptographic algorithms, including microarchitecture definition, simulation, and synthesis. Model and integrate the high-level architecture with external IP (e.g., RISC-V), tune protections against side-channel attacks, and prepare verification inputs for FPGA and ASIC workflows. Collaborate with the ASIC backend team and support technical documentation and certification activities.

Responsibilities

• Design and implement RTL for cryptographic algorithms resistant to quantum attacks

• Define microarchitecture, run simulations, and synthesize digital designs

• Model high-level architecture and integrate external IP (e.g., RISC-V)

• Tune protections against side-channel attacks

• Prepare input data for the FPGA and ASIC verification environment

• Create technical documentation and participate in certification processes

• Collaborate with the ASIC backend engineering team

Requirements

• Higher education in Electrical Engineering, Computer Engineering, or a related field

• Minimum 5 years of FPGA design and development experience for Mid level (or 8 years for Senior)

• Fluency in VHDL, Verilog, or SystemVerilog for RTL design

• Knowledge of the ASIC design process

• Experience with timing analysis, synthesis, and implementation

• Hands-on experience with fast interfaces/protocols such as PCIe, Ethernet, and AXI

• Experience integrating systems, including embedded processors

• EU citizenship

• Analytical thinking and ability to solve complex problems

Benefits

• Broad technical responsibility for the solutions you build

• Equity options

• Work on innovative projects with high importance for security

• Opportunity to participate in closed events with defense-sector stakeholders