Senior RTL Design Engineer

Mueon

18m ago • On-site

Mid

On-site

120,000 - 200,000 USD/yr

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Quick Facts

  • Role: Senior RTL Design Engineer

  • Focus: Hands-on RTL development for complex digital IP and SoC subsystems for next-generation AI computing platforms

Description

You will design and develop synthesizable RTL using Verilog and SystemVerilog, translating architectural and microarchitecture specifications into efficient, high-performance, low-power hardware. You will partner with architects, verification, physical design, and DFT teams to deliver production-ready, silicon-ready IP, while meeting aggressive timing, power, area, and schedule goals.

Responsibilities

  • Design and develop synthesizable RTL for complex digital IP blocks and SoC subsystems

  • Translate architecture into efficient high-performance, low-power implementations

  • Collaborate with verification to develop plans, review functional coverage, and resolve issues

  • Run module/block simulation, debugging, and functional validation

  • Drive RTL quality via lint, CDC, and RDC analysis and fixes

  • Work with synthesis and physical design to optimize timing, power, area, and manufacturability

  • Support DFT integration (scan implementation and RTL modifications for test)

  • Participate in design and code reviews and technical discussions

  • Support post-silicon bring-up, debug, and root-cause analysis

  • Contribute to RTL methodologies, coding standards, automation, and reusable infrastructure

Requirements

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience

  • 3–5 years of experience developing RTL for ASIC or FPGA designs

  • Strong proficiency with Verilog and/or SystemVerilog

  • Solid understanding of digital logic design, synchronous design techniques, and computer architecture

  • Experience with simulation tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, or equivalent

  • Familiarity with lint, CDC, and RDC verification methodologies

  • Working knowledge of synthesis, static timing analysis, DFT, and physical implementation flows

  • Experience with scripting languages such as Python, Tcl, or Perl

  • Strong analytical, debugging, and communication skills

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