FPGA Design Engineer

Quick Facts

FPGA RTL design role for cryptographic, quantum-attack-resistant algorithms, including security hardening and verification support across FPGA and ASIC.

Description

Design and implement RTL at the block and subsystem level for cryptographic algorithms resistant to quantum attacks. Define microarchitecture, run simulation and synthesis, model high-level architecture, and integrate with external IP such as RISC-V. Strengthen the design against side-channel attacks and prepare inputs for FPGA and ASIC verification environments, contributing to technical documentation and certification activities.

Responsibilities

• Design and implement RTL for cryptographic algorithm blocks and subsystems.
• Define microarchitecture; perform simulations and digital design synthesis.
• Model high-level architecture and integrate external IP (e.g., RISC-V).
• Tune protections against side-channel attacks.
• Prepare input data for FPGA verification and ASIC verification environments.
• Create technical documentation and participate in certification processes.
• Collaborate with the ASIC backend team.

Requirements

• Higher education in Electrical Engineering, Computer Engineering, or a related field.
• Mid: minimum 5 years of FPGA design/development experience; Senior: minimum 8 years.
• Fluent in VHDL, Verilog, or SystemVerilog for RTL design.
• Knowledge of the ASIC design process.
• Experience with timing analysis, synthesis, and implementation.
• Practical knowledge of high-speed interfaces and protocols such as PCIe, Ethernet, and AXI.
• Experience integrating systems, including embedded processors.
• Analytical thinking and ability to solve complex problems.
• European Union citizenship.

Benefits

• Broad technical responsibility for the developed solutions.
• Equity options.
• Work on innovative, security-critical projects.
• Opportunity to attend closed events with defense-sector representatives.