Senior Verification Engineer (ASIC & Networking)

Quick Facts

• Role: Senior Verification Engineer (ASIC & Networking)

Description

You will own verification planning and execution for complex ASIC/SoC blocks and subsystems for a high-throughput modem and DSP-intensive digital beamformer. You will translate design specifications into verification strategies with measurable coverage goals, build verification environments (reference models, scoreboards, monitors, assertions), and drive coverage closure using constrained-random simulation and formal methods. You will also help build an AI-enabled verification platform for stimulus generation, regression triage, and data-driven coverage analytics.

Responsibilities

• Own verification planning through sign-off for complex blocks/subsystems
• Convert design specifications into verification strategy, measurable coverage goals, and early identification of high-risk scenarios
• Select verification methods (constrained-random simulation, formal analysis, directed testing)
• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions
• Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results
• Build verification infrastructure, regression and CI systems, and reuse strategy across IP/subsystem/SoC
• Apply and build AI-assisted verification for stimulus generation, regression triage, and coverage analytics
• Review testbench architecture and debug methodology; mentor junior engineers in verification methodology

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience
• Minimum 5 years of professional ASIC or SoC functional verification
• Hands-on SystemVerilog and UVM or formal testbench development and maintenance
• Experience with metric-driven verification for planning, assertions, and functional coverage closure
• Experience verifying complex digital control and datapath logic, including RTL and system-level debug

Benefits

• Opportunity to help define verification strategy, methodology, and infrastructure for first in-house silicon (target first tapeout in 2027)
• Work across IP, subsystem, and full SoC verification, including high-speed datapaths and mixed-signal interfaces
• Build and grow AI-enabled verification capabilities such as LLM-assisted stimulus/testbench generation, automated regression triage, and coverage analytics