ASIC Verification Engineer (New Grad 2027)

Quick Facts

• Role: ASIC Verification Engineer (New Grad 2027)
• Focus: Pre-silicon RTL design verification, simulation-based validation, and debugging

Description

Contribute to ASIC design verification activities that support the pre-silicon process by simulating RTL under a variety of conditions to surface design bugs early. Build and improve verification environments using UVM, create directed or random SystemVerilog tests to validate reference C++ and RTL models, and debug RTL simulation failures. The role also emphasizes automation for verification workflows.

Responsibilities

• Create automated verification systems and flows
• Contribute to complex UVM testbench environments (test development, automation, or analysis)
• Develop directed or random SystemVerilog tests to verify reference C++ and RTL models in simulation
• Debug RTL simulation failures

Requirements

• Pursuing or recently completed BS, MS, or PhD in EE, CE, or related field (or equivalent experience)
• Coursework or internship exposure to computer architecture, logic design, and/or HDL languages (Verilog, VHDL)
• Strong programming experience in C++ or SystemVerilog and general understanding of OOP concepts
• Solid understanding of basic CPU or SoC architecture
• Exceptional analytical and problem-solving skills

Benefits

• Eligible for equity and benefits
• Base salary range: $100,000–$166,750 (Level 1) or $116,000–$189,750 (Level 2), depending on location and experience