Senior Verification Engineer (High-Speed Coherent Interconnect)

Quick Facts

• Role: Senior Verification Engineer (High-Speed Coherent Interconnect Hub IP)
• Focus: ASIC verification for coherency protocol, interoperability, and performance

Description

You will work with architecture and design teams to verify complex High Speed Coherent Interconnect Hub IP, helping define verification strategies and environments. Responsibilities include functional and performance verification, coverage closure, and driving signoff for high-quality design completion.

Responsibilities

• Develop and maintain verification infrastructure (testbenches, BFMs, checkers, monitors, scoreboards, assertions, constrained-random stimulus)
• Define and complete verification test plans for coherency protocol, ordering, error handling, and performance-related IP features
• Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces
• Develop and complete performance test plans (bandwidth, latency, QoS, and other performance requirements)
• Drive functional and code coverage closure and support verification signoff
• Debug complex RTL and verification issues and coordinate resolution with architecture/design teams
• Collaborate with FPGA, emulation, software, and post-silicon teams to support system validation and silicon bring-up

Requirements

• BS/MS (or equivalent experience)
• 3+ years of ASIC verification experience with complex IPs or SoC subsystems
• Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification
• Experience building verification environments with checkers, assertions, and functional coverage
• Strong debugging and problem-solving skills using industry-standard simulation and debug tools

Benefits

• Competitive salary with base pay range: $136,000–$218,500 (Level 3) or $168,000–$264,500 (Level 4), depending on location and experience
• Equity and generous benefits package