Senior Analog Mixed-Signal Design Verification Engineer

Quick Facts

• Role: Senior Analog Mixed-Signal Design Verification Engineer

Description

You will lead mixed-mode design verification methodology, defining the co-simulation EDA environment and the approach to simulate complex SOCs. You will create Verilog/SystemVerilog testbenches and behavioral models for analog and mixed-signal circuits, develop block- and chip-level mixed-mode verification methodologies, and support model bring-up with analog and digital teams. The role includes performing AMS simulations.

Responsibilities

• Define the co-simulation methodology and EDA infrastructure with analog and digital teams

• Create Verilog/SystemVerilog testbenches and behavioral models of analog and mixed-mode circuits

• Develop block- and chip-level mixed-mode verification methodologies

• Support analog and digital teams during model bring-up and usage

• Perform AMS simulations

Requirements

• MS in Computer Engineering or Electrical Engineering

• 5+ years of relevant industry experience

• Hands-on experience in CMOS analog mixed-signal circuit design and verification

• Verilog/SystemVerilog modeling of functional behavior of analog/mixed-signal circuits and systems

• Proficient with EDA tools and environments such as Cadence Virtuoso for schematic creation and simulation

• Proficient with scripting/programming languages such as Python and MATLAB

• Strong communication skills

Benefits

• Culture focused on safety, collaboration, and inclusion

• Work on mission-driven space technology for reusable, safe, and low-cost space systems