Senior ASIC Design Engineer

Quick Facts

• Senior ASIC Design Engineer focused on SoC/GPU RTL delivery and verification

Description

You will document, implement, and deliver fully verified, high-performance, area and power-efficient RTL to meet design targets and specifications. Responsibilities include architecture and micro-architecture design, RTL design and synthesis, and logic and timing verification, while contributing to verification scope and verification infrastructure. You will collaborate across multiple ASIC development teams and coordinate with members in remote locations.

Responsibilities

• Deliver fully verified, high performance, area and power efficient RTL
• Perform architecture and micro-architecture design
• Develop RTL, run synthesis, and verify logic and timing
• Participate in verification methodology work; help define verification scope
• Support development of verification infrastructure
• Collaborate and coordinate with other ASIC teams, including remote members

Requirements

• Bachelors or Masters degree (or equivalent experience)
• 5+ years of relevant work experience
• Proven hardware engineering background in VLSI and computer architecture
• Expert knowledge of Verilog/SystemVerilog (or similar HDL)
• Proficient in Perl/Python (or similar scripting languages)
• Experience with logic synthesis and timing analysis
• Experience with ASIC design and verification tools (e.g., VCS, Verdi, GDB)
• Experience creating testbenches for unit and system-level verification
• Random stimulus with functional coverage and assertion-based verification experience (strong plus)
• Strong debugging and analytical skills
• Ability to work with on-site and remote teams

Benefits

• Equity and benefits eligibility
• Base salary range varies by level and location: Level 3 (136,000–218,500 USD) and Level 4 (168,000–264,500 USD)