Senior ASIC Design Verification Engineer

Quick Facts

• Role: Senior ASIC Design Verification Engineer

Description

Hands-on verification role to validate the functionality, performance, and robustness of custom ASIC designs. You will define the verification approach, develop SystemVerilog/UVM environments, and drive simulation-based validation with coverage closure. You’ll collaborate across RTL, DFT, firmware, physical design, and silicon validation to resolve issues and support silicon bring-up.

Responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments

• Build SystemVerilog/UVM testbenches (agents, monitors, scoreboards, checkers, coverage models)

• Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate

• Drive constrained-random and directed tests for corner cases and stress scenarios

• Run simulations, triage failures, and perform root-cause analysis with RTL teams

• Implement and maintain functional, code, and assertion coverage; ensure coverage closure for sign-off

• Manage regression testing, simulation farms, and CI pipelines for throughput and fast debug

• Participate in design reviews and influence design-for-verification (DFV) best practices

• Support silicon bring-up and post-silicon validation using test reuse and diagnostics

• Contribute to DV methodology advancement and improvements

• Engage external IP providers and verification partners when needed

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related field

• 5+ years of ASIC/SoC verification experience

• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows

• Proficiency with simulation tools, waveform debug tools, coverage tools, and scripting (Python/Perl/Tcl)

• Experience with UVM testbench development, constrained-random testing, functional coverage, and SVA

• Experience with regression management, coverage analysis, Git, and CI/CD automation

• Understanding of industry interfaces such as APB/AHB/AXI

• Familiarity with embedded processor-based designs and firmware/bare metal coding (C/C++)

Benefits

• Base salary range: $170,000–$250,000 + equity

• Paid time off and comprehensive medical/dental/vision coverage

• Life insurance and paid parental leave

• Additional perks and compensation based on skills, education, and experience