Advanced ASIC/FPGA Verification Engineer

Quick Facts

• Role: Advanced ASIC/FPGA Verification Engineer
• Work setup: Fully remote, on-site, or hybrid/flex (mutually agreed)
• Primary focus: RTL simulation and verification using SystemVerilog and UVM

Description

Define, design, verify, and document ASIC and/or FPGA developments by establishing verification architecture, detailed simulation approach, and test plans. Build UVM testbench components and verify results through functional coverage, assertions, and constrained-random testing (with optional formal verification). Analyze performance, debug issues, and contribute to verification process improvements in a mission-focused engineering environment.

Responsibilities

• Determine verification architecture and system simulation strategy
• Define module interfaces and simulation details
• Create test and simulation plans with functional criteria
• Verify outcomes, analyze performance, and report/resolve issues
• Develop UVM environments (agents, bus functional models, predictive components)
• Work with coverage (cover classes/points) and assertions (SVA)
• Support process improvements across the ASIC/FPGA development life cycle
• May provide leadership or direction to lower-level employees

Benefits

• Flexible 9/80 schedule option with every other Friday off
• 401k matching, flex time off, paid parental leave
• Healthcare benefits and health & wellness programs
• Employee resource and social groups
• Continuous learning and development opportunities

Requirements

• Bachelor’s degree in Electrical/Computer Engineering (or related) with 5+ years of job-related experience, or a Master’s degree with 3+ years
• Ability to obtain a U.S. DoD TS/SCI security clearance within a reasonable time after hire
• U.S. citizenship required

Hard Skills & Technologies

• SystemVerilog
• UVM
• Questa
• ModelSim
• RTL simulation
• Linux
• constrained random
• functional coverage
• assertions
• SVA
• predictive testbench
• coverage points
• Register Abstraction Layer
• formal verification
• code coverage
• waivers
• TCL
• Python
• GitLab
• AXI
• PCIe
• Space Wire
• Ethernet
• Xilinx
• QVIP
• VHDL