Principal Design Verification Engineer

Quick Facts

Principal Design Verification Engineer (Design or DV)

Description

Lead a subsystem as a design or design verification engineer on an AI System on Chip (AISoC) team. Collaborate across architecture, design, DV, firmware, and post-silicon teams to debug system-level issues and deliver silicon from concept through bring-up. Drive either design quality closure (CDC/lint/RDC) and performance/power/area tradeoffs or DV strategy and execution using UVM-based constrained-random verification with functional coverage closure.

Responsibilities

• Technically lead a subsystem as a design or DV engineer
• Collaborate across teams on vertical and horizontal reuse of components
• Provide technical leadership through mentorship and strong teamwork
• Work with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues
• Deliver silicon from concept through bring-up
• Understand and work on complex subsystems (e.g., PCIe, HBM, imaging, control), fabrics, AMBA AXI/CHI, DMA engines, NoCs, and high-throughput data buffering/movement

Requirements

• Doctorate in a relevant field plus 3+ years technical engineering experience, OR Master’s plus 6+ years, OR Bachelor’s plus 8+ years (or equivalent experience)
• Ability to meet security screening requirements and pass the Microsoft Cloud background check
• Eligibility to access export-controlled information (citizenship/residency verification as required)

Benefits

• Base pay range across the U.S.: USD $142,800–$274,800 per year
• Different location-specific base pay ranges may apply (e.g., San Francisco Bay area and NYC metro: USD $188,000–$304,200 per year)
• Eligible for benefits and other compensation (per employer compensation information)