Silicon Front-End CAD Verification Engineer

Quick Facts

• Role: Silicon Front-End CAD Verification Engineer (front-end DV)

• Focus: Verification flows for ASICs/FPGAs from IP testbench to SoC regression

• Location: Austin, Texas (on-site)

Description

You will shape silicon front-end verification by architecting scalable DV environments, developing reusable SystemVerilog/UVM testbenches and VIP, and advancing IP-to-SoC methodology across simulation, formal, and coverage closure. You’ll also apply AI tools to accelerate testbench creation, debug, and regression triage, and deliver production-ready automation for regression and release qualification using Jenkins CI and OneRun.

Responsibilities

• Architect scalable DV environments with layered, reusable SystemVerilog/UVM testbenches and clear separation

• Develop high-quality UVM VIP with protocol checking, coverage, and low simulation overhead

• Advance verification methodology across constrained-random and directed simulation, assertions, formal, and coverage closure

• Use and improve AI tools (e.g., ChipAgents, Kiro) for testbench creation and regression triage

• Automate regression and release qualification in Jenkins CI and OneRun; run controlled pilots on real designs

• Address complex flow/tool issues, influence EDA vendor improvements, and mentor engineers

Benefits

• Competitive salary (range dependent on experience and other factors) plus opportunity for an annual bonus

• Choice of medical plan options and dental plan; company credits toward premiums

• 401(k) with automatic 3% contribution and matching for eligible contributions

• Company credits for life insurance and disability coverage; Stock Purchase Plan option

• Minimum 15 days accrued vacation, personal days, annual holidays, volunteer time, and sick time; paid parental/maternity leave options

• Additional company-paid benefits including financial wellness programs and educational assistance