Principal ASIC Verification Engineer (Silicon Design Verification)

Quick Facts

• Role: Principal ASIC Verification Engineer (Silicon Design Verification)

• Team: Data Processing Unit (DPU)

• Focus: Pre-silicon and post-silicon functional validation of complex ASIC SoCs

Description

As a Principal Engineer in the DPU team, you will validate silicon to solve complex datacenter problems. You will lead functional validation of complex ASIC SoCs using UVM/C testbenches, define pre-silicon verification and post-silicon validation strategies, and execute testing, debugging, and performance/stress scenarios. You will also participate in chip bring-up and write test firmware while collaborating across architecture, design, verification, and partner teams.

Responsibilities

• Lead key components of functional validation for complex ASIC SoCs using UVM/C

• Define test strategies for pre-silicon SoC verification and post-silicon validation

• Develop test plans, C tests, and validation infrastructure; report bugs/issues

• Run tests, debug failures, and create stress/performance scenarios to meet test goals

• Collaborate cross-functionally to influence next-generation design execution

• Participate in chip bring-up and write test firmware for supporting teams

• Improve validation efficiency via methodologies and tools

• Coach and mentor others in verification expertise

Requirements

• Doctorate with 3+ years technical engineering experience OR Master’s with 6+ years OR Bachelor’s with 8+ years (or equivalent)

• Meet security screening requirements, including Microsoft Cloud background check (upon hire/transfer and every two years)

• Provide proof of citizenship or U.S. residency/protected status to access export-controlled information

Benefits

• Base pay range (U.S.): USD $142,800 - $274,800 per year

• Base pay range in San Francisco Bay Area / NYC metro: USD $188,000 - $304,200 per year

• Eligible for benefits and other compensation (varies by role/location)