Principal ASIC Design Verification Engineer

Quick Facts

Hands-on principal-level ASIC/SoC verification role focused on custom silicon validation, coverage closure, and driving first-generation bring-up.

Description

Define and execute verification strategies for block, subsystem, and full-chip environments to validate functionality, performance, and robustness of custom ASIC designs. Build UVM/SystemVerilog testbenches with agents, monitors, scoreboards, checkers, and coverage models, using SVA and (where applicable) formal verification. Own regression execution and debug workflows, then collaborate cross-functionally to close coverage for sign-off and support silicon bring-up.

Responsibilities

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments
• Build SystemVerilog/UVM testbenches (agents, monitors, scoreboards, checkers, coverage models)
• Write SystemVerilog Assertions (SVA) and integrate formal verification when appropriate
• Drive constrained-random and directed testing for corner cases and stress scenarios
• Run simulations, triage failures, and lead root-cause analysis with RTL partners
• Implement and maintain functional, code, and assertion coverage; ensure coverage closure for sign-off
• Manage regressions, simulation farms, and CI pipelines for high throughput and fast debug
• Participate in design reviews and influence design-for-verification (DFV) best practices
• Support silicon bring-up and post-silicon validation using test reuse and diagnostic/debug analysis
• Lead large/complex verification efforts; advance DV methodologies
• Manage external IP/verification partners when needed
• Participate in ASIC team interviews

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related field
• 10+ years of ASIC/SoC verification experience
• Solid understanding of SystemVerilog, RTL design, DFT, and hardware verification flows
• Proficiency with UVM-based verification: test planning, constrained-random testing, functional coverage
• Experience with SVA; ability to integrate formal verification when appropriate
• Experience with simulation tools (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), and coverage tools
• Strong scripting skills (Python, Perl, TCL) for DV automation
• Experience with regression management, coverage analysis, Git, CI/CD automation, and gate-level simulation
• Experience developing and integrating reference models
• Experience with embedded processor-based designs and firmware/bare-metal coding (C/C++)
• Knowledge of common interfaces (APB/AHB/AXI)
• Involvement in post-silicon validation planning and execution

Benefits

• Base salary range: $190,000 – $285,000 + company equity
• Comprehensive benefits: paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and other perks