Principal SoC Hardware Analog/Functional Validation Engineer

Quick Facts

• Role: Principal SoC Hardware (Analog/Functional) Validation Engineer

• Focus: Post-silicon validation, debug, and test automation for custom SoCs

Description

Own post-silicon validation for PCIe/IO functional or electrical/analog interface areas, including debug, triage, and failure analysis. Define validation strategy, requirements, environments, and tools; develop test plans and test content/scripts to validate functional behavior and power/performance characteristics. Provide technical leadership and guidance across validation planning, pre-silicon debug, and hardware/software debug.

Responsibilities

• Own post-silicon validation for PCIe, IO functional IO, or electrical/analog interfaces

• Define and implement silicon debug tools and capabilities

• Become an expert in high-speed IO interfaces (e.g., PCI, CXL, PLL) and their interactions across the SoC, platform, and software

• Coach and mentor engineers in relevant expertise areas

• Develop validation strategy, requirements, environments, tools, and methodologies (including debug board and hardware/software requirements)

• Write test plans and implement them by developing test content, scripts, tools, and other validation collateral

• Execute content in post-silicon, triage, and debug failures

• Develop sophisticated tools/scripts to support debug (e.g., maximum power, current transients, register dumps)

• Collaborate with partners to improve design and validation plans/methodology to prevent, reduce, and/or find bugs earlier

• Collaborate across architects, logic designers, verification engineers, other post-silicon validators, and IP/tool providers

• Apply expertise to pre-silicon verification plans, tests, and debug for the area

Requirements

• Doctorate/PhD with 3+ years experience OR Master’s with 6+ years OR Bachelor’s with 8+ years (or equivalent)

• Ability to meet Microsoft/customer/government security screening requirements, including passing the Microsoft Cloud Background Check and export-controlled eligibility requirements

• Applied understanding of computer architecture and CPU/SoC validation principles, including ability to write scripts/software in Python or C/C++

• Verification/logic development/analog validation or validation tools experience in CPU/SoC/IP development teams

• Demonstrated validation expertise in one or more: functional IO (PCIe, CXL, USB), electrical (Serdes, IO, high speed interconnect, analog circuits), power and performance, automation/content/tools/scripts development

• Ability to develop synthetic SoC validation content for both bare metal and OS environments

• Understanding of board-level schematics and system-level software/firmware

• Hands-on silicon failure debugging using on-chip debug features (trace/JTAG) and test equipment (oscilloscopes, protocol analyzers, bit error rate testers, logic analyzers)

Benefits

• Base pay range (U.S.) typically USD $142,800–$274,800/year; San Francisco Bay Area and New York City metro typically USD $188,000–$304,200/year (location-dependent)

• Eligible for benefits and other compensation (see company pay information)