Principal Silicon Design Verification Engineer

Quick Facts

• Role: Principal Silicon Design Verification Engineer

Description

Lead functional validation of PCIe IP at the Block, Cluster, or Fullchip level using UVM-based test benches and Verification IP (VIP). Own test plan creation, unit test development, and regression suite management including debug and coverage goals to support tapeout. Improve validation efficiency through new methodologies and tools.

Responsibilities

• Functional validation of PCIe IP at Block, Cluster or Fullchip using UVM/C test bench and Verification IP (VIP)

• Develop test plan and write unit tests for functional validation

• Create and manage regression suites, debug failures, and drive timely resolution

• Innovate to improve validation efficiency through methodologies and tools

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience; or Master’s AND 6+ years; or Bachelor’s AND 8+ years; or equivalent experience

• Ability to meet Microsoft, customer and/or government security screening requirements, including passing the Microsoft Cloud background check upon hire/transfer and every two years thereafter

• Eligibility to access export-controlled information (provide proof of country of citizenship or U.S. residency/other protected status; citizenship verified with a valid passport)

Benefits

• Competitive base pay range (U.S.): USD $142,800–$274,800 per year

• Base pay range for San Francisco Bay Area and New York City metro: USD $188,000–$304,200 per year

• Certain roles may be eligible for benefits and other compensation