Principal RTL Methodology and Design Engineer

Quick Facts

• Role: Principal RTL Methodology and Design Engineer

• Focus: RTL methodology and static signoff (lint/CDC/RDC) with hands-on RTL design

• Location: Austin, Texas (not remote)

Description

Own how RTL is written and signed off—from coding rules through lint, CDC, and RDC signoff criteria. Combine hands-on RTL design with methodology leadership to build vendor-agnostic, reusable static signoff flows that measurably improve RTL quality, IP reuse, and time to a qualified netlist.

Responsibilities

• Define RTL design methodology: coding guidelines, lint rule sets, waiver policy, and signoff criteria for IP, subsystem, and SoC teams; govern changes and mentor engineers.

• Lead lint, CDC, and RDC signoff: architect structural, formal, and hybrid CDC/RDC flows with progressive goals and hierarchical signoff using abstract models and clock/reset constraints; keep criteria tool-independent.

• Build vendor-agnostic flows: deliver single-command static signoff in OneRun with standard project templates and Jenkins CI quality gates; qualify rule mapping between vendor tools.

• Drive RTL reuse and automation: architect configurable RTL frameworks and standard interfaces for multi-program IP reuse; set strategy for next-generation register generation to produce signoff-clean RTL.

• Apply AI to RTL engineering: use and improve ChipAgents and Kiro for development, documentation, code conversion, and lint/CDC triage; evaluate against manual baselines with engineering review.

• Strengthen FE-BE handoff: define RTL quality, SDC, and UPF checks for netlist handoff with synthesis, DFT, and back-end teams; roll out through representative pilots without disrupting tapeout schedules.

Requirements

• 10+ years in ASIC/SoC RTL design and front-end methodology with evidence of production deployment and successful tapeout contributions.

• Deep hands-on SystemVerilog/Verilog RTL design and microarchitecture for complex IP/SoC blocks, including parameterized and low-power design with UPF.

• Strong experience with Synopsys VC SpyGlass and/or Cadence JasperGold for lint, CDC, and RDC; understanding of synthesis, timing, and DFT dependencies.

• Strong Python and scripting skills; experience building maintainable automation with Linux, version control, code review, CI, automated tests, and controlled releases.

• Proven ability to set standards, explain technical trade-offs, and lead across distributed teams.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.

Benefits

• Competitive compensation with bonus opportunity tied to business and individual performance.

• Excellent health benefits: choice of three medical plans and a dental plan, with employee premium credits.

• Financial security benefits: US 401(k) with automatic contribution and matching, plus life insurance, disability coverage, and an optional stock purchase plan.

• Time-off benefits including accrued vacation, personal days, annual holidays, volunteer time, sick time, and paid maternity/parental leave options.

• Additional benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.