Senior Principal Application Engineer (RTL to GDSII)

Quick Facts

• Role: Senior Principal Application Engineer (RTL to GDSII)

• Focus: Hands-on backend digital design implementation and signoff

Description

You will work hands-on with customers on backend digital design implementation and signoff, spanning synthesis, place and route, design closure, and timing/power signoff from RTL to GDSII. You will lead technical campaigns in RTL-to-GDSII implementation, aggressively improve Power, Performance, and Area (PPA), and deliver technical presentations and discussions with both customers and internally. You will also collaborate with R&D to enhance tools and methodologies and support critical customer tape-outs.

Responsibilities

• Lead RTL to GDSII digital implementation activities including synthesis, place and route, design closure, and timing/power signoff

• Drive strategies and technical campaigns to improve PPA

• Present and discuss technical topics internally and with customers

• Partner with R&D to enhance tools and methodologies to meet/exceed customer requirements

• Support critical customer flagship product tape-outs

• Amend and augment implementation flows using Tcl and/or other scripting to meet objectives and improve results

Requirements

• MS in CS/Engineering, Electrical Engineering, or related field plus 10+ years industry experience

• Strong digital design fundamentals, semiconductor fundamentals, and Static Timing Analysis

• Backend IC implementation experience including synthesis, place and route, IR drop, backend timing and power closure, and RTL to GDSII

• Scripting experience in Perl/Tcl/Python for automation and process improvement

• Floorplanning and power planning experience for low-power SoC designs

• Experience with front-end flows including synthesis, DFT, and Logical Equivalence Checking

• Strong hands-on floorplanning, place and route, timing analysis, and signoff (preferably with Cadence tools suite)

• Advanced clock tree synthesis: SoC clock distribution, clock mesh, H-tree

• Multiple design closure experience (timing, DRC, LVS, EMIR) preferred

• Experience with advanced technology nodes (Sub 5nm and below)

• Ability to develop, debug, and optimize SoC design flow aspects to achieve best PPA

• Strong customer-facing communication and problem-solving skills

• Strong verbal and written communication skills and continuous learning mindset

• Cadence tool experience (Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus) highly desired

Benefits

• Annual salary range (California): $148,400 to $275,600

• Potential incentive compensation: bonus, equity, and benefits

• Paid vacation and paid holidays

• 401(k) with employer match

• Employee stock purchase plan

• Medical, dental, and vision plan options (and more)