Principal Design Engineer

Quick Facts

• Role: Principal Design Engineer (Digital Logic / ASIC / SoC)

Description

Deliver premium-quality silicon designs by developing custom IP and System-on-Chip (SoC) digital logic, from microarchitecture through RTL implementation. Own logic design and RTL for high-performance digital IP, drive design quality (lint, CDC, RDC, power), and support timing closure and optimization. Collaborate with verification and other engineering teams (including physical design and DFT) and provide technical leadership through mentorship.

Responsibilities

• Develop cutting-edge custom IP and SoC designs
• Create solutions for complex, high-performance functions with exceptional efficiency
• Own logic design and Register Transfer Level (RTL) implementation for high-performance digital IP
• Drive design quality across lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power, and related design requirements
• Support timing closure and optimization of high-performance digital IP
• Collaborate with verification teams to ensure implementations meet architectural and microarchitectural intent
• Partner with Physical Design (PD) and Design for Test (DFT) to evaluate and optimize design tradeoffs
• Provide technical leadership through mentorship, collaboration, and teamwork

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field plus 3+ years technical engineering experience OR
• Master’s degree plus 6+ years technical engineering experience OR
• Bachelor’s degree plus 8+ years technical engineering experience OR equivalent experience
• Ability to meet security screening requirements, including passing the Microsoft Cloud background check, and requirements for access to export-controlled information

Benefits

• Base pay range (U.S.): USD $142,800–$274,800 per year (Bay Area and NYC metro ranges differ)
• Eligible for benefits and other compensation (details provided by employer)