Principal Silicon Design Engineer

Quick Facts

• Role: Principal Silicon Design Engineer (Custom IP / FPGA prototyping)
• Focus: FPGA design environment, custom IP RTL, verification, post-silicon validation, and design signoff

Description

Own and lead FPGA design environment efforts for rapid IP prototyping and design validation, including root-cause analysis of complex system issues. Develop custom IP RTL from microarchitecture through RTL implementation, verification, and post-silicon validation while collaborating across architecture, SoC, firmware, verification, and physical design teams. Drive PPA optimization and lead signoff activities such as CDC, RDC, LINT, and timing closure.

Responsibilities

• Lead FPGA design environment work for rapid IP prototyping and design validation
• Develop custom IP RTL from microarchitecture to implementation, verification, and post-silicon validation
• Collaborate with cross-functional teams (architecture, SoC, firmware, verification, physical design)
• Build high-performance, power-efficient RTL and drive PPA optimization
• Lead design signoff: CDC, RDC, LINT, and timing closure
• Mentor engineers and improve design excellence via reviews, automation, and methodology enhancements

Requirements

• Doctorate with 3+ years engineering experience, or Master’s with 6+ years, or Bachelor’s with 8+ years (or equivalent experience)
• Ability to meet security screening requirements including Microsoft Cloud Background Check (and re-screening every two years)
• Ability to access export-controlled information; provide proof of citizenship or US residency/other protected status (e.g., via passport)

Benefits

• Typical base pay range (U.S.): USD $142,800–$274,800 per year (with different ranges for SF Bay Area and NYC)
• Role may be eligible for benefits and other compensation; additional details available via the company careers pay page