Senior Silicon Design Engineer

Microsoft

Redmond, WA • 15m ago • Hybrid

Senior

Hybrid

119,800 - 234,700 USD/yr

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Potential salary for Senior Silicon Design Engineer role

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$119,800 – $234,700/year

Quick Facts

  • Role: Senior Silicon Design Engineer (custom IP / silicon design)
  • Focus: RTL ownership, verification, signoff, PPA optimization, and post-silicon validation

Description

Own development of custom IP RTL from microarchitecture through verification and post-silicon validation. Collaborate across architecture, SoC, firmware, verification, and physical design teams to deliver high-quality, high-performance, power-efficient IP. Lead signoff activities (CDC, RDC, LINT, synthesis, STA, timing closure), drive pre- and post-silicon debug/root-cause analysis, and mentor engineers through design-excellence reviews and automation.

Responsibilities

  • Own custom IP RTL development (microarchitecture → RTL implementation → verification → post-silicon validation)
  • Collaborate with architecture, SoC, firmware, verification, and physical design teams
  • Develop high-performance, power-efficient RTL designs and drive PPA optimization
  • Lead design signoff: CDC, RDC, LINT, synthesis, STA, timing closure
  • Design hardware algorithms for acceleration of key data processing operations
  • Drive pre-silicon/post-silicon debug, silicon bring-up, and root-cause analysis
  • Mentor engineers and champion design excellence via reviews, automation, and methodology improvements

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year technical engineering experience, OR
  • Master’s degree AND 4+ years, OR
  • Bachelor’s degree AND 5+ years, OR equivalent experience
  • Ability to meet Microsoft, customer, and/or government security screening requirements (including passing the Microsoft Cloud background check)
  • Ability to access export-controlled information; provide required proof of citizenship/U.S. residency/protected status
  • 3+ years experience in digital logic design (SystemVerilog/Verilog/VHDL)
  • 3+ years experience running synthesis/static check tools (RTL synthesis, lint, CDC, RDC, and/or LEC)

Benefits

  • Base pay range (U.S.): USD $119,800–$234,700 per year
  • Base pay range (San Francisco Bay area / NYC metro): USD $160,200–$261,000 per year
  • Eligible roles may receive benefits and other compensation (details via Microsoft pay information page)

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