Senior ASIC/FPGA Design Engineer (Digital Hardware / Defense)

Quick Facts

• Role: Senior ASIC/FPGA Design Engineer (Digital Hardware / Defense)

• Focus: Lead digital hardware design, development, and verification across the ASIC/FPGA life cycle

• Clearance: U.S. citizenship required; must be able to obtain DoD TS/SCI clearance

Description

Lead end-to-end ASIC/FPGA digital hardware design and verification for complex defense engineering programs. Own the full development flow—from digital architecture and system simulation through synthesis, place and route, timing analysis, power optimization, and verification planning—while providing technical leadership to multidisciplinary teams. Deliver technical documentation, present engineering decisions and verification results, and support feasibility assessments and subcontract oversight.

Responsibilities

• Define, design, verify, and document ASIC/FPGA solutions across the hardware development life cycle

• Develop digital hardware architectures, module interfaces, system simulations, and detailed design approaches

• Evaluate implementation workflows (synthesis, place and route, timing analysis, power utilization) and assess performance/power outcomes

• Create test and simulation plans; define functional verification criteria; analyze test results and design performance

• Evaluate foundry technologies, device libraries, simulation tools, and vendor capabilities

• Produce engineering deliverables (technical plans, specifications, design documentation, and customer-facing work products)

• Present requirements, design concepts, engineering decisions, and verification results to internal teams and external customers

• Support technical subcontract management (SOWs, proposal evaluation, source selection, technical oversight, deliverable acceptance)

• Lead technical feasibility assessments using customer proposals, specifications, and engineering documentation

• Apply engineering standards and development procedures across the ASIC/FPGA product life cycle

• Identify and implement improvements to engineering processes, methodologies, and workflows

• Contribute to engineering estimates and technical approaches for proposals and initiatives

• Lead technical tasks for small teams; mentor junior engineers

• Use EVM concepts and metrics (SPI, CPI, CAM) and SPC for project planning and performance management

• Communicate technical risks, impacts, and corrective actions with engineering management, teams, customers, and vendors

• Identify opportunities to apply AI to improve engineering processes and productivity

Requirements

• U.S. citizenship (federal requirement)

• Ability to obtain a DoD Top Secret/Sensitive Compartmented Information (TS/SCI) security clearance within a reasonable period following hire

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related STEM with 8+ years of relevant experience; or Master’s degree with 6+ years

• Advanced knowledge of ASIC/FPGA engineering, digital hardware design processes, and verification methodologies

• Experience with ASIC/FPGA architecture, system simulation, detailed design, and module interface development

• Understanding of synthesis, place and route, timing analysis, and power utilization workflows

• Experience building verification plans, analyzing simulation results, and evaluating digital hardware performance

• Ability to evaluate technical specifications, component reliability, and vendor capabilities for hardware feasibility

• Experience writing technical documentation, engineering specifications, and design presentations/customer deliverables

• Knowledge of project leadership and metrics: EVM, SPI/CPI, CAM, SPC

• Ability to communicate engineering decisions, technical risks, performance impacts, and corrective actions

• Proficiency with Microsoft Office

Benefits

• Pay estimated: $89.48–$94.48 per hour

• Opportunity to lead critical digital hardware programs across the full ASIC/FPGA development life cycle