FPGA Verification Engineer

Quick Facts

• Role: FPGA Verification Engineer

• Focus: RTL verification for cryptographic FPGA/crypto processor blocks

• Level: Mid (5+ years) or Senior (8+ years)

Description

You will create and maintain block- and subsystem-level verification plans for cryptographic algorithms and processors. You’ll design reusable modular verification environments and simulation setups for complex IP blocks, then perform functional and code-coverage analysis with thorough documentation. You will also collaborate with the ASIC backend team to troubleshoot verification and design issues.

Responsibilities

• Develop and maintain verification plans at block and subsystem level for cryptographic algorithms and processors

• Design and implement reusable modular test environments

• Build simulation environments for verifying complex IP blocks

• Perform functional analysis and code-coverage analysis

• Debug verification and design problems with engineers

• Maintain technical documentation, including test plans, coverage reports, and bug logs

• Collaborate with the ASIC backend team

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or related field

• Minimum 5 years of FPGA verification/design development experience (Mid) or 8+ years (Senior)

• Strong RTL verification knowledge with VHDL, Verilog, or SystemVerilog

• Knowledge of the ASIC design flow

• Experience with tools such as VUnit, cocotb, or UVM

• Ability to work independently and with a cross-functional team

• Strong analytical skills and problem-solving ability

Benefits

• Work on projects building the foundations of secure electronics

• Flexible working hours

• Option packages (equity)

• Broad technical responsibility and growth opportunities