Principal ASIC/FPGA Design Engineer (Digital Hardware)

Moseley Technical Services, Inc.

Scottsdale, AZ • 2h ago • On-site

Senior

On-site

224,640 - 235,040 USD/yr

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Quick Facts

  • Role: Principal ASIC/FPGA Design Engineer (Digital Hardware)
  • Focus: ASIC/FPGA development life cycle and technical leadership for defense programs
  • Security: U.S. citizenship required; ability to obtain DoD Top Secret/TS/SCI clearance

Description

Lead advanced ASIC/FPGA digital hardware design, development, and verification across the full hardware development life cycle for complex defense engineering programs. Own hardware architecture, simulation, synthesis, place-and-route, timing analysis, and power optimization, while defining verification plans and providing technical leadership for proposals and feasibility assessments. Manage technical oversight for subcontracts and deliver engineering outputs aligned with established standards.

Responsibilities

  • Define, design, verify, and document ASIC and FPGA solutions throughout the life cycle
  • Establish digital hardware architectures, module interfaces, and system simulations
  • Evaluate implementation workflows: logic synthesis, place and route, timing analysis, and power utilization
  • Develop test and simulation plans, set functional verification criteria, analyze results, and evaluate performance
  • Assess semiconductor foundry technologies, device libraries, simulation tools, and vendor capabilities
  • Lead technical subcontract management including SOWs, proposal evaluations, and deliverable acceptance
  • Develop and improve ASIC/FPGA processes, standards, procedures, and technical workflows
  • Generate technical engineering deliverables per established development standards and organizational processes
  • Perform technical feasibility assessments for proposals, specifications, and application requirements
  • Select hardware components and equipment based on technical specifications and reliability requirements
  • Support technical proposal approaches and coordinate for medium-sized opportunities
  • Participate in Integrated Product Teams (IPTs) and engineering working groups
  • Provide technical supervision and mentoring to junior engineers and teams
  • Resolve unusually complex design and development challenges and manage engineering scope objectives
  • Apply engineering project management principles (SPI, CPI, EVM, CAM, SPC)
  • Serve as a technical consultant to engineering management and customers; may support DPME activities
  • Identify opportunities to apply AI to improve engineering processes and innovation

Requirements

  • U.S. citizenship required
  • Ability to obtain DoD Top Secret/TS/SCI security clearance within a reasonable period after hire
  • Bachelor’s degree with 10+ years relevant experience, or Master’s degree with 8+ years relevant experience
  • Extensive experience with ASIC/FPGA digital hardware design, development processes, and verification methodologies
  • Demonstrated expertise in ASIC/FPGA architecture, system simulation, detailed hardware design, and module interface development
  • Experience evaluating synthesis, place and route, timing analysis, and power utilization workflows
  • Experience developing verification plans and evaluating hardware performance from simulation/test results
  • Ability to evaluate engineering specifications, semiconductor technologies, vendor capabilities, and feasibility
  • Knowledge of engineering standards, organizational processes, and development methodologies in complex hardware programs
  • Experience with technical subcontract management and proposal/vendor evaluation processes
  • Understanding of project leadership principles including SPI/CPI, Earned Value Management (EVM), Cost Account Management (CAM), and Statistical Process Control (SPC)
  • Ability to manage scope growth and solve unusually complex technical challenges
  • Ability to present recommendations, risks, and corrective actions to management and customers
  • Proficiency with Microsoft Office applications

Benefits

Not specified in the provided posting.

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