Senior Physical Design CAD Equivalency Engineer

Quick Facts

• Role: Senior Physical Design (PD) CAD Equivalency Engineer

• Focus: Formal equivalency checking and low-power (UPF-aware) verification for advanced-node silicon

Description

You will own and evolve formal equivalency CAD flows that prove functional correctness before tapeout, including RTL-to-netlist, netlist-to-netlist, functional ECO, and UPF-aware low-power verification. You will develop and maintain production flows and automation using Tcl and Python for Synopsys Formality and Cadence Conformal, partnering with design teams and EDA vendors to qualify tools and resolve critical issues.

Responsibilities

• Own end-to-end formal equivalency CAD flow (RTL-to-netlist, netlist-to-netlist, functional ECO, and low-power UPF-aware verification)

• Develop, debug, and maintain production equivalency flows and automation in Tcl and Python (including complex design classes)

• Partner with physical design, front-end/synthesis, signoff teams, and EDA vendors to qualify tool releases and support tapeout closure

• Drive technical decisions, identify root causes of ambiguous tool behavior, and mentor teammates

• Deliver measurable improvements in flow quality, runtime, and reliability (regression coverage, documentation, support turnaround)

Requirements

• Doctorate AND 1+ year technical engineering experience, OR Master’s AND 4+ years, OR Bachelor’s AND 5+ years (or equivalent experience)

• Ability to meet Microsoft security screening requirements, including the Microsoft Cloud Background Check

• Eligibility to access export-controlled information; provide proof of citizenship or U.S. residency/protected status (valid passport required)

Benefits

• Competitive base pay range (U.S.): USD $119,800–$234,700 per year (varies by location, including San Francisco Bay area and NYC metro)

• Additional benefits and compensation may apply