Principal Design Verification Engineer

Quick Facts

• Role: Principal Design Verification Engineer

• Focus: Hardware verification for cloud compute silicon and interconnect subsystems

Description

Own or lead functional and performance verification for one or more aspects of Fabric Top subsystem integration, including coherency, traffic flows to/from memory, and PCIe/CXL endpoint end-to-end interconnect functionality. Partner with architecture, design, and verification teams to define verification strategies, test plans, and signoff criteria. Build and enhance UVM and/or Formal verification environments, automation for performance measurement and debug, and drive bug discovery and root-cause analysis.

Responsibilities

• Lead verification for Fabric Top subsystem integration (coherency, memory traffic, PCIe/CXL endpoints, end-to-end interconnect)

• Define verification strategies, test plans, and signoff criteria with cross-functional teams

• Develop and enhance UVM and/or Formal verification environments, performance measurement tools, automation infrastructure, and reusable collateral

• Drive bug discovery and root-cause analysis using simulation, formal analysis, assertions, coverage, and debug

• Improve verification productivity through automation, methodologies, and AI-driven solutions

• Coach and mentor engineers on verification methodologies and best practices

Requirements

• Doctorate (Electrical Engineering, Computer Engineering, Computer Science, or related) + 3+ years technical engineering experience, or Master’s + 6+ years, or Bachelor’s + 8+ years, or equivalent experience

• Ability to meet security screening requirements, including the Microsoft Cloud Background Check

• Provide proof of citizenship or valid US residency/protected status to access export-controlled information

Benefits

Eligible for benefits and other compensation (per company pay/benefits information link).