Senior Design Verification Engineer (Fabric Interconnect)

Quick Facts

• Role: Senior Design Verification Engineer (Fabric Interconnect)

• Focus: Integration-level verification of Fabric Top (coherency, PCIe/CXL traffic, configuration access)

Description

Own and/or lead integration-level verification of Fabric Top, including coherency (e.g., CHI), PCIe/CXL traffic, and configuration access. Build UVM/SystemVerilog verification environments, run and debug simulations, and develop verification strategies and test plans with partner IP/SOC and VIP teams. Improve verification efficiency using automation, formal-based methods, and AI/generative AI approaches.

Responsibilities

• Lead integration-level verification for Fabric Top, spanning coherency, PCIe/CXL traffic, and configuration access traffic

• Collaborate with partner IP/SOC teams and VIP teams to define verification strategies and test plans

• Develop UVM/SystemVerilog verification environments; run and debug simulations to drive quality

• Use automation, formal-based methods, and AI-based approaches to enhance verification

• Innovate with methodologies or tools to improve verification efficiency

• Apply generative AI solutions to verification work

• Coach and mentor others in areas of expertise

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related + 1+ year technical engineering experience, OR

• Master’s degree + 4+ years technical engineering experience, OR

• Bachelor’s degree + 5+ years technical engineering experience, OR equivalent experience

• Ability to pass required security screening (including Microsoft Cloud Background Check every two years)

• Eligibility to access export-controlled information (provide proof of citizenship or US residency/eligible protected status)

Benefits

• Competitive base pay range (varies by U.S. location)

• Eligibility for benefits and other compensation

• Career support through ongoing application process until the role is filled