Senior DSP Fixed-Point Design Engineer

Quick Facts

• Role: Senior DSP Fixed-Point Design Engineer (Silicon Development)

Description

You will convert floating-point DSP algorithm models into bit-true, cycle-accurate fixed-point architectures and validate them for aerospace silicon. The role focuses on precision and quantization noise analysis, defining hardware-friendly DSP architecture (pipeline/word lengths/rounding/overflow and scaling), and partnering with RTL and design verification teams for pre- and post-silicon validation. You will also drive micro-architectural optimizations for low power, high throughput, and minimal silicon area.

Responsibilities

• Build fixed-point, bit-true cycle-accurate models from floating-point algorithms using MATLAB, C++, or Python

• Perform quantization noise, finite word-length, and area/power/performance trade-off analyses to manage SNR/EVM degradation

• Specify and document fixed-point DSP architectures (pipeline structures, rounding modes, saturation/overflow, scaling)

• Collaborate with RTL teams to review implementations of DSP hardware blocks and ensure bit-true correctness

• Generate test vectors and golden reference models to support DV and post-silicon validation

• Optimize micro-architecture for power, throughput, and area for custom accelerators

• Coordinate across systems engineering, avionics, and software teams to meet end-to-end system requirements

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or a related field

• 5+ years of hands-on silicon/ASIC/FPGA development experience with DSP hardware implementation

• Strong fixed-point expertise (quantization noise modeling, overflow/underflow handling, dynamic range management, scaling)

• Expert proficiency in MATLAB, C++, and/or Python (NumPy/SciPy)

• Solid DSP fundamentals (FIR/IIR filter design, FFT architectures, multi-rate processing, AGC)

• Ability to clearly document and communicate technical trade-offs

Benefits

• Work on flight-critical aerospace silicon that meets demanding reliability and performance standards

• Opportunity to bridge algorithm-to-hardware implementation and influence silicon optimization decisions