FPGA/Digital Lead Engineer

Quick Facts

• Role: FPGA/Digital Lead Engineer

Description

Lead the design and development of the FPGA-based digital section of a radar system—covering everything from waveform generation to received-signal processing. Implement radar waveform and DSP processing in hardware, including range compression and matched filtering, while managing system timing and synchronization. Develop and integrate high-speed data interfaces (e.g., JESD204B) and support system testing, bring-up, and validation.

Responsibilities

• Generate radar waveforms, including LFM chirps on the DAC

• Acquire and sample data from the ADC

• Synchronize and manage system timing

• Implement range compression and matched filtering in FPGA

• Control PRF and TX/RX sequencing

• Implement DSP functions, FFT, and data-stream processing

• Develop FPGA interfaces using JESD204B

• Integrate the FPGA with mass storage and other system components

• Participate in system tests, startup, and validation

Requirements

• 5+ years of FPGA design experience (preferably for radar, SDR, or high-throughput systems)

• Very good knowledge of VHDL or SystemVerilog

• Knowledge of Python

• Experience with Vivado, Quartus, and ModelSim (or comparable tools)

• Practical DSP knowledge: FFT and matched filtering

• Experience with DMA and large data stream processing

• Knowledge of JESD204B

• Ability to work with technical documentation in English

Benefits

• Opportunity to build the digital system architecture from scratch

• Real impact on key technology decisions

• Work on advanced radar system development