Design Verification Engineer (Fabric Interconnect)

Quick Facts

• Role: Design Verification Engineer (Fabric Interconnect)

Description

You will own integration-level verification of a Fabric Top design, covering coherency (CHI), PCIe/CXL traffic, and configuration access traffic. You’ll develop UVM/SystemVerilog verification environments, run and debug simulations, and coordinate with partner IP/SOC and VIP teams to define verification strategies and test plans. You’ll also use automation, formal methods, and generative AI to improve verification efficiency and quality.

Responsibilities

• Own aspects of integration-level verification of Fabric Top (coherency, PCIe/CXL traffic, configuration access traffic)

• Learn about the design and collaborate with partner IP/SOC teams and VIP teams to define verification strategies and test plans

• Develop UVM/SystemVerilog verification environments at the integration level and run/debug simulations to drive quality

• Leverage automation, formal-based methods, and AI-based approaches

• Innovate to improve verification efficiency through methodologies or tools

• Apply generative AI solutions to verification work

• Coach and mentor others in your areas of expertise

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years technical engineering experience

• OR Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience (or equivalent experience)

• Ability to meet required security screening (including Microsoft Cloud Background Check)

• Ability to access export-controlled information (citizenship or U.S. residency/protected status verification)

Benefits

• Typical base pay range (U.S.): USD $102,100 - $202,200 per year (San Francisco Bay area / NYC metro: USD $133,800 - $219,200)

• Benefits and other compensation may be available for eligible roles

• Applications accepted on an ongoing basis until the position is filled