Design Verification Engineer

Quick Facts

• Role: Design Verification Engineer (pre-silicon hardware validation)

Description

You will plan verification for complex design IPs and work with architecture and design engineers to define verification scenarios. You will build constrained-random verification environments with SystemVerilog and UVM (or perform formal verification with SVA and formal tools), develop tests, debug failures, and write functional coverage to close verification gaps for tape-out.

Responsibilities

• Plan verification of complex design IPs interacting with architecture and design teams

• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify using SVA and formal tools

• Develop tests using UVM or C/C++

• Analyze and debug test failures with designers

• Identify and write functional coverage for stimulus and corner cases

• Close coverage to plug verification holes and meet tape-out requirements

• Collaborate cross-functionally with Architecture, Design, Verification, and Firmware

• Support chip bring-up and write test firmware

• Improve validation efficiency via new methodologies and tools

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ years technical engineering experience, OR Bachelor’s degree AND 2+ years technical engineering experience, OR equivalent experience

• Ability to meet security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years

• Ability to access export-controlled information and provide proof of citizenship or U.S. residency/status (verified via valid passport)

Preferred Qualifications

• 3+ years related technical engineering experience (or equivalent degree + 3+ years / internship experience)

• Experience executing full-cycle pre-silicon verification for IPs/subsystems/SoCs

• Background creating and debugging IP/SoC-level tests in SV-UVM/C

• In-depth knowledge of verification principles, testbenches, and stimulus generation

• Solid understanding of silicon chip and/or computer architecture

• Experience with formal verification methods

• Experience in assembly, start up code, linker scripts

• Experience developing Makefiles for software development