Senior FPGA and Silicon Design Engineer

Quick Facts

• Role: Senior FPGA and Silicon Design Engineer

• Focus: Custom IP RTL and FPGA prototyping/validation for cloud chip development

Description

Own and lead FPGA design environment efforts for rapid custom IP prototyping and validation, including root-cause analysis. Develop custom IP RTL from microarchitecture through verification and post-silicon validation, collaborate across SoC/firmware/verification/physical design teams, and drive PPA optimization and signoff (CDC/RDC/LINT/timing). Mentor engineers and improve design methodology through reviews, automation, and continuous improvement.

Responsibilities

• Own and lead FPGA design environment efforts for rapid IP prototyping and design validation, including root-cause analysis of complex system issues.

• Develop custom IP RTL from microarchitecture through RTL implementation, verification, and post-silicon validation.

• Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality FPGA and IP solutions.

• Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle.

• Lead design signoff activities including CDC, RDC, LINT, and timing closure.

• Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements.

Requirements

• PhD plus 1+ year technical engineering experience, or Master’s plus 4+ years, or Bachelor’s plus 5+ years in Electrical Engineering, Computer Engineering, Computer Science, or related field (or equivalent experience).

• Meet Microsoft/customer/government security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

• Access export-controlled information eligibility; provide proof of citizenship or valid U.S. residency/protected status (passport-based verification as required).

Preferred Qualifications

• 4+ years in digital logic design using SystemVerilog/Verilog/VHDL.

• 4+ years running synthesis/static check tools including RTL synthesis, lint, CDC, RDC, and/or LEC.

• Expertise in digital design, microarchitecture specification development, and FPGA implementation.

• 5+ years of FPGA and RTL design experience.

• Experience reading/writing Python code.

• Experience optimizing high-speed CMOS designs with power/performance/area tradeoff analysis.

• Experience with Xilinx FPGA boards and tooling.

• Experience with ChipWhisperer or similar FPGA power analysis tools.

• Experience setting up test automation infrastructure and results checking.

Benefits

• Base pay range (U.S.): USD $119,800–$234,700 per year

• San Francisco Bay area and New York City metro: USD $160,200–$261,000 per year

• Eligibility for benefits and other compensation may apply.