Pre-Silicon Digital Verification Engineer

Quick Facts

Pre-silicon digital verification engineer position focused on mixed-signal integrated circuits verification.

Description

• Verify complex digital IPs within a mixed-signal ASIC environment by translating block specifications into clear, precise verification plans.
• Build and own verification testbenches using formal verification and UVM-based simulation.
• Develop testcases with SystemVerilog Assertions and constrained-random UVM tests to achieve functional and code coverage.
• Collaborate with system architects and digital designers on specifications, debugging, and code reviews to improve the likelihood of bug-free tapeouts.
• Track tapeout readiness using functional and code coverage; debug test failures and work with designers on fixes.
• Explore additional verification techniques including formal verification, digital mixed-signal verification, and analog mixed-signal simulation with state-of-the-art tools.

Requirements

• Minimum: bachelor’s degree in a related field.
• Preferred: extensive coursework in digital design and computer architecture.
• Preferred: foundation in object-oriented programming.
• Preferred: lab courses or work experience with SystemVerilog.
• Preferred: familiarity with constrained-random verification techniques.
• Preferred: familiarity with clock-domain crossing design and verification.
• Preferred: some coursework in analog circuit design.

Benefits

Benefits are not specified in the provided posting.