Principal Analog Mixed-Signal Design Verification Engineer

Quick Facts

• Role: Principal Analog Mixed-Signal Design Verification Engineer

Description

Lead the mixed-mode design verification methodology by defining a co-simulation EDA environment and the approach to simulate complex SOCs. Build Verilog/SystemVerilog testbenches and behavioral models for analog and mixed-mode circuits, and develop block- and chip-level mixed-mode verification. Support model bring-up and usage and perform AMS simulations.

Responsibilities

• Define the co-simulation methodology and EDA infrastructure working with analog and digital teams
• Create Verilog/SystemVerilog test benches and behavioral models of analog and mixed-mode circuits
• Develop methodologies for block- and chip-level mixed-mode verification
• Support analog and digital teams during model bring-up and usage
• Perform AMS simulations

Requirements

• MS in Computer or Electrical Engineering
• 10+ years of relevant industry experience
• Hands-on experience in CMOS analog mixed-signal circuit design and verification
• Verilog/SystemVerilog modeling of functional behavior of analog/mixed-signal circuits and systems
• Proficient using EDA tools and environments such as Cadence Virtuoso for schematic creation and simulation
• Proficient with scripting/programming languages such as Python and MATLAB
• Strong communication skills

Benefits

The posting highlights a culture of safety, collaboration, and inclusion, with opportunities to contribute to mission-driven space systems.