Senior SoC Hardware (Analog/Functional) Validation Engineer

Quick Facts

• Role: Senior SoC Hardware (Analog/Functional) Validation Engineer (technical individual contributor)

• Focus: Post-silicon functional and/or power/performance validation for custom SoC projects

Description

Own post-silicon validation for PLL, IO electrical/analog, and/or functional IO interfaces. Define validation strategies and requirements, build debug tools and test collateral, and execute triage/debug for silicon failures. Provide deep expertise in high-speed IO interface architecture and guide other engineers through technical leadership and mentorship.

Responsibilities

• Own post-silicon validation in one or more areas: PLL, IO electrical/analog, or functional IO interfaces

• Define, guide, and contribute to silicon debug tools and capabilities

• Develop expertise in high-speed IO architectures (e.g., PLL, PCI, CXL) and their SoC/platform/software interactions

• Develop validation strategies, requirements, environments, tools, and methodologies

• Create test plans; implement tests via test content, scripts, tools, and validation collateral

• Execute post-silicon validation; triage and debug failures

• Develop synthetic SoC validation core/content for bare-metal and OS environments

• Develop tools/scripts for debug (e.g., maximum power, current transients, register dumps)

• Provide technical guidance, coaching, and mentorship to other engineers

• Support pre-silicon verification plans, tests, and debug of your area

• Partner with stakeholders to improve design, validation plans/collateral, and methodologies to find bugs sooner and more reliably

Requirements

• Doctorate with 1+ years experience OR Master’s with 4+ years OR Bachelor’s with 5+ years OR equivalent experience in a relevant field (Electrical Engineering, Computer Engineering, Computer Science, or related)

• Ability to meet security screening requirements, including the Microsoft Cloud Background Check

• Eligibility to access export-controlled information, with citizenship or US residency/protected status verification

Benefits

• Competitive base pay range in the U.S.: USD $119,800–$234,700 (with higher ranges for specific locations such as San Francisco Bay Area and New York City metro)

• Potential eligibility for benefits and other compensation