Senior Physical Design Verification Engineer

Quick Facts

• Role: Senior Physical Design Verification Engineer

Description

You will work on physical design verification for leading-edge semiconductor technology nodes, including analysis and fixes for LVS, DRC, ERC, and antenna-related issues. You will drive full-chip integration for physical design verification signoff and tape-outs, collaborating with clock, analog, and integration teams on routing, power delivery, and block integration. You will also partner with IP teams and CAD/tool vendors to develop and validate verification tools, flows, and runsets, using scripting/AI to improve efficiency and productivity.

Responsibilities

• Collaborate with physical design engineers on analysis and fixes for LVS, DRC, ERC, Antenna, and related issues

• Drive full-chip physical design verification signoff and tape-outs on leading-edge technology nodes

• Partner with clock, analog, and integration teams to define, implement, and verify critical routing, power delivery, and block integration

• Coordinate with 3pIP and 1pIP teams for SoC-IP handshake

• Work with CAD, tool vendors, foundry, and external partners to develop and validate new tools, flows, and runsets

• Use scripting/AI to write and customize tool flows to maximize design efficiency and productivity

Requirements

• PhD in Electrical Engineering/Computer Engineering/Computer Science (or related) plus 1+ year technical engineering experience, or Master’s plus 4+ years, or Bachelor’s plus 5+ years (or equivalent experience)

• Ability to meet security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter

• Ability to access export-controlled information (citizenship/US residency/status verification required)

Benefits

• Base pay range (U.S.): USD $119,800–$234,700 per year (with location-dependent ranges for specific metros)

• Potential eligibility for benefits and other compensation per company pay information