Silicon Front-End CAD Engineer

Quick Facts

• Role: Silicon Front-End CAD Engineer (Developer)

• Focus: Extend OneRun, a Python-based front-end CAD flow platform

• Location: Austin, Texas (not remote)

Description

Shape the platform silicon engineers use every day to simulate, verify, check, and emulate ASIC and FPGA designs. Build and evolve OneRun by extending its architecture, plugins, and APIs, integrating and piloting new tool/flow bring-ups, and enabling emulation workflows. Deliver measurable improvements in flow runtime, compute/license efficiency, onboarding time, and engineering productivity.

Responsibilities

• Evolve OneRun: extend architecture, plugins, and APIs in clean, well-tested Python; keep tool abstractions vendor-agnostic so flows run unchanged across Cadence and Synopsys tools.

• Bring up pilot flows: script and integrate new tools/flows, pilot on real IP and SoC designs, and promote to production after meeting acceptance criteria.

• Enable emulation through OneRun: add emulation compile/run/debug into OneRun so teams move from simulation to emulation with the same setup and workflow.

• Optimize performance and usability: reduce runtime/startup overhead and compute & license usage; improve onboarding via templates, clear error messages, and documentation.

• Apply AI to CAD engineering: use and improve AI tools (e.g., Kiro and ChipAgents) for spec-driven development, flow debug, and first-line user support; validate against reproducible baselines with engineering review.

• Deliver production-ready capabilities: automate OneRun regression testing and release qualification in Jenkins CI; support controlled rollout; resolve complex flow issues with users and EDA vendors.

Requirements

• 5+ years in front-end CAD, EDA flow development, or silicon infrastructure software with evidence of production deployment supporting ASIC or FPGA projects.

• Strong Python software engineering skills (modular design, APIs, automated testing with PyTest or equivalent), plus Linux, Git, code review, CI, and controlled releases.

• Hands-on experience integrating front-end EDA tools (e.g., Xcelium, VCS, JasperGold, VC SpyGlass), including tool configuration, licensing, and compute farms such as LSF.

• Working knowledge of ASIC/SoC design and verification flows, SystemVerilog, and UVM.

• Ability to turn recurring user problems into reusable platform features and collaborate effectively in distributed teams.

• Bachelor’s or master’s degree in CS/EE/CE or related field, or equivalent practical experience.

• Critical exposure: emulation experience (e.g., Siemens Veloce or Cadence Palladium) and practical AI/ML or LLM-based tool use for automation/debug/user support; building vendor-agnostic EDA frameworks; or measurable improvements in runtime/compute efficiency/adoption.

Benefits

• Competitive salary range dependent on factors such as location and experience.

• Annual bonus opportunity under a short-term variable compensation plan.

• Excellent health benefits with multiple medical and dental options plus company credits toward premiums.

• 401(k) plan with automatic company contribution and matching on employee contributions.

• Life insurance, accidental death and dismemberment coverage, and disability coverage; option to participate in stock purchase plan.

• Work-life balance benefits including at least 15 days accrued vacation, personal days, annual holidays, volunteer time, sick time, and paid parental leave options.

• Additional company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.