Design-for-Test (DFT) Engineer (ASIC Backend)

Quick Facts

• Role: Design-for-Test (DFT) Engineer (ASIC Backend)

• Focus: DFT architecture, verification, and post-silicon validation for advanced ASICs

• Work setting: 100% onsite (El Segundo or Huntington Beach, CA)

• Clearance: U.S. Secret clearance required; U.S. citizenship required

Description

Design and validate test access mechanisms for leading-edge ASICs, including TAP/JTAG, IJTAG (IEEE 1687), boundary scan, MBIST, scan compression, and related test infrastructure. You will develop and verify DFT architectures, generate and optimize ATPG patterns, validate memory tests, and support scan and at-speed silicon debug and bring-up. You will also integrate DFT features across the chip design flow and collaborate with cross-functional and external partners when required.

Responsibilities

• Design and implement DFT architectures: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression

• Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation

• Drive pattern generation, coverage optimization, memory test validation, and silicon debug (scan, at-speed, bring-up)

• Integrate DFT features across the chip design flow and collaborate with cross-functional teams for robust integration

• Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable

• Contribute to development and deployment of DFT methodologies for next-generation products

• Occasional travel and after-hours meetings during critical milestones

Requirements

• Ability to obtain a U.S. Security Clearance requiring U.S. citizenship

• Interim and/or final U.S. Secret clearance post-start

• Bachelor of Science degree in a relevant field (Engineering, CS, Data Science, Math, Physics, Chemistry or non-US equivalent)

• 2+ years of experience in DFT or equivalent

• Strong knowledge of ASIC/logic design flow, Verilog/SystemVerilog HDL, static timing analysis, and ECO processes

• Hands-on expertise with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug

• Proficiency in Tcl/Perl/Python scripting and DFT verification methodologies

• Excellent analytical, problem-solving, and communication skills

Benefits

• Competitive base pay and variable compensation opportunities

• Eligible employees may enroll in health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance, and paid/unpaid time away from work

• Relocation support based on candidate eligibility