Logic Design Engineer

Quick Facts

• Role: Logic Design Engineer

Description

Design and own logic blocks for advanced memory-subsystem components, working within complex IP “fabrics” and bridging IPs. You will be responsible for the full design flow—from RTL coding and lint/CDC checks to timing closure—while collaborating with verification, performance modeling, physical design, and DFT teams to optimize tradeoffs. You’ll also develop automation and AI-based solutions to improve organizational efficiency.

Responsibilities

• Develop advanced components of the memory sub-system

• Build automation and AI-based solutions to improve organizational efficiency

• Own design blocks within complex, coherent fabrics, and bridge IPs

• Handle the end-to-end design flow (RTL coding, lint, CDC, timing closure, etc.)

• Define interfaces and make optimal design choices with the team

• Partner with verification teams to create test plans and ensure functional correctness

• Coordinate with performance modeling, physical design, and design-for-test teams to optimize tradeoffs

Requirements

• 5+ years of related technical engineering experience, or a degree with the corresponding years of experience as specified in the posting

• 3+ years of digital logic design experience for ASIC or FPGA

• Ability to meet security screening requirements, including the Microsoft Cloud Background Check and eligibility to access export-controlled information

Benefits

• Base pay range (U.S. typical): USD $102,100–$202,200 per year; other ranges apply for specific locations (e.g., San Francisco Bay area and New York City metro)

• Eligible for benefits and other compensation (details provided via the company pay/benefits page)