Memory Subsystem Design Engineer (RTL, Place-and-Route)

Quick Facts

• Role: Memory Subsystem Design Engineer (RTL, Place-and-Route)

• Focus: Large memory blocks and memory subsystem development

Description

Design and architect memory subsystems for large memory blocks, implementing RTL and delivering physical design (place and route). Own design closure activities across timing, DRC, LVS, and EM/IR sign-off, and support gate netlist synthesis and verification (including logical equivalency checks). Use Python and automation scripting to streamline tool flows and improve execution.

Responsibilities

• Architect and design memory subsystems

• Implement RTL of subsystem designs

• Perform place and route (physical design)

• Drive design closure: timing, DRC, LVS, EM/IR, etc.

• Perform gate netlist synthesis

Requirements

• Minimum 8 years of relevant experience

• Bachelor’s degree in Electrical Engineering

• Strong design skills and ability to write/debug Verilog RTL

• Place-and-route expertise

• Proficient in running STA, DRC, EM/IR tools and achieving design closure

• Ability to code in Python

• Understanding of synthesis tools and experience running synthesis

• Ability to run and debug logical equivalency checkers

• Familiarity with memory behavior

Benefits

• Discretionary annual bonus

• New hire equity grant and annual equity awards (subject to plan documents)

• Medical, dental, vision

• 401(K) with company matching

• ESPP

• Employee Assistance Program (EAP)

• Company-paid holidays; paid sick leave and vacation

• Paid Family Leave and other leaves of absence (per applicable law)

• Base salary range: USD 109,700.00 to USD 175,500.00