Principal Silicon Engineer

Quick Facts

• Role: Principal Silicon Engineer

Description

Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into clean, efficient, high-quality hardware implementations. Lead design intent capture and validation for digital and mixed-signal blocks, ensuring accurate constraints and integration across front-end and physical design flows. Provide static timing leadership for mixed-signal interfaces and partner cross-functionally to resolve timing, power, and functional issues.

Responsibilities

• Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems
• Lead capture and validation of design intent for digital and mixed-signal blocks
• Provide static timing leadership for mixed-signal interfaces (timing closure and exception quality, correlation across MMMC corners)
• Partner with RTL, PD, mixed-signal, DFT, and CAD teams on cross-domain integration
• Contribute to design automation using AI, constraint checking, and flow improvements to improve execution efficiency and PPA
• Operate with limited direction; communicate status, risks, and mitigation plans to program leadership

Requirements

• Doctorate in EE/CE/CS or related field with 3+ years technical engineering experience, OR Master’s with 6+ years, OR Bachelor’s with 8+ years (or equivalent experience)
• Must meet Microsoft/customer/government security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
• Must be eligible to access export-controlled information; provide proof of citizenship or US residency/status and undergo passport-based citizenship verification

Benefits

• Certain roles may be eligible for benefits and other compensation
• Base pay range (U.S.): USD $142,800–$274,800 per year
• Base pay range (SF Bay area / NYC metro): USD $188,000–$304,200 per year