Digital Design Verification Engineer

Quick Facts

• Role: Digital Design Verification Engineer
• Focus: UVM testbench setup and design verification for large designs

Description

You will help establish UVM-based testbenches for design verification on large designs. The role requires high autonomy from initial specification through timing closure and physical design hand-off, and cross-functional collaboration with Architecture, Verification, and Physical Design teams.

Responsibilities

• Set up and operate design verification testbenches using UVM on large designs
• Drive tasks autonomously from initial specification through timing closure and physical design hand-off
• Collaborate cross-functionally to mitigate risks and ensure project milestones are met on schedule

Requirements

• BSEE required; MSEE/PhD preferred
• 5+ years of industry experience focused on SoC integration, UVM testbench setup, and design debug
• High proficiency in UVM

Benefits

• Discretionary annual bonus
• New hire equity grant and annual equity awards (subject to plan documents)
• Medical, dental, and vision plans
• 401(K) with company matching; ESPP
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence per applicable laws