HBM Datapath Architect

Quick Facts

• Role: HBM Datapath Architect (Staff Design Engineer, HBM Architecture)

Description

The HBM Architecture team develops advanced datapath solutions for next-generation High Bandwidth Memory (HBM) products. In this role, you will architect, design, and optimize high-speed data paths for logic-die and core-die architectures across JEDEC and custom HBM solutions, collaborating with design, PHY, ECC, verification, layout, and system groups.

Responsibilities

• Architect and design HBM read and write datapath across core and logic die (alignment, buffering, timing, and control logic)
• Develop high-speed, low-latency datapath circuits for multi-channel HBM architectures and wide internal buses
• Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes
• Design and integrate data reliability features (parity, ECC hooks, lane redundancy, remapping mechanisms)
• Collaborate cross-functionally to translate specifications into micro-architectures
• Work with PHY, DFT, verification, and layout teams to ensure accurate functionality, testability, and manufacturability
• Drive schematic-level and RTL-level datapath implementations (clocking, gating, reset strategies)
• Contribute to design reviews, documentation, and technical mentoring
• Use AI-enabled tools (e.g., Microsoft Copilot and other approved AI solutions) to improve productivity and streamline problem solving

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 7+ years relevant experience, or Master’s degree with 5+ years relevant experience
• 3+ years experience in high-speed digital datapath design (memory, SerDes, or SoC datapath)
• 3+ years hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations

Benefits

• Choice of medical, dental, and vision plans
• Income protection benefits for illness or injury
• Paid family leave
• Robust paid time-off and paid holidays