Principal ASIC Synthesis and Timing Engineer

Quick Facts

• Role: Principal ASIC Synthesis and Timing Engineer

Description

Lead the implementation of complex SoCs for next-generation satellite and space systems by owning the RTL-to-synthesis flow and driving timing closure through sign-off. Develop and maintain PPA optimization methodologies, ensure clean handoffs between RTL/verification and physical design, and build an end-to-end formal verification methodology for full confidence from RTL to post-layout netlist. Manage external physical design partners and collaborate across teams to achieve first-pass silicon success in advanced FinFET technologies.

Responsibilities

• Own the complete RTL-to-Synthesis flow (block and top-level synthesis) and integrate physical synthesis floorplanning information.

• Develop and maintain design methodologies, scripts, and automation to optimize PPA.

• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient iteration.

• Drive timing closure across multiple voltage and process corners and perform foundry-qualified sign-off.

• Own Lint, CDC, and UPF checks; drive issue resolution.

• Develop an end-to-end formal verification methodology with no gap between RTL and the post-layout netlist.

• Manage and technically guide external physical design partners and service vendors for schedule, deliverables, and quality.

• Work with EDA vendors to debug and optimize tool flows and evaluate new methodologies.

• Support chip bring-up and debug with post-silicon and test teams.

• Support production and spaceflight through ongoing design/product readiness.

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or related field

• 10+ years of ASIC design experience for high-performance SoCs

• Proven end-to-end RTL-to-GDSII expertise using industry tools (Synopsys, Cadence, or Siemens)

• Strong hands-on timing closure, IR drop analysis, low power implementation, and ECO implementation experience

• Deep understanding of physical design constraints for multi-clock, multi-voltage, hierarchical SoCs

• Experience with advanced FinFET process nodes

• Prior experience resolving formal verification issues

• Ability to analyze and fix VCLP issues related to UPF

Benefits

• Base salary range: $190,000–$280,000 + equity

• Paid time off

• Medical/dental/vision coverage

• Life insurance

• Paid parental leave