Chip Package Signal and Power Integrity Engineer

Qualifications

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with SI/PI design for chip/package or system PCB.
• Experience with industry Signal Integrity and Power Integrity (SI/PI) modeling toolchains, such as HFSS, ADS, Sigrity, and Siwave.

Preferred qualifications:

• Master’s degree or PhD in Electrical Engineering or SI/PI.
• Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die stacking technologies, with SI/PI analysis expertise for high-speed interconnects.
• Knowledge of next-generation memory and chiplet standards, including timing budgets and design and sign-off methodologies.
• Understanding of Static Timing Analysis, on-chip DVD/EMIR, system voltage budgets, and voltage regulator modeling and design.
• Ability to lead cross-functionally across chip design, physical design, STA, packaging, system, and validation teams.
• Proficiency in Python, Matlab, or C++ for automation flows and advanced data processing and analysis.

Description

In this role, you will help shape AI/ML hardware acceleration and drive TPU technology for demanding AI/ML applications. You will develop custom silicon solutions and contribute design and verification expertise for complex digital designs, with a focus on TPU architecture and its integration in AI/ML-driven systems.

As a Chip Package Signal Integrity/Power Integrity (SI/PI) Engineer on the chip implementation team, you will be responsible for chip-package design, SI/PI simulation, and characterization at package and system level. You will work with system architects, ASIC engineers, SI/PI engineers, chip and board design teams, system design teams, and vendors to deliver chip packaging signal and power implementations that meet chip, package, and system electrical requirements.

Responsibilities

• Drive chip-package-system co-design through SI/PI analysis and optimization, contributing to product definition and optimizing chip floorplans, power-tree structures, and netlists for HPC using 2.5D/3D package technology.
• Develop power-integrity methodologies for advanced package technology and improve methodology accuracy and productivity.
• Evaluate new package technologies and high-speed interface IP.
• Collaborate with chip design, system design, and supplier teams to establish chip-package SI/PI targets, define chip-design boundaries, and explore SI/PI and DFM trade-offs for package design closure in production.
• Provide feedback on chip floorplans based on package and system routability and SI/PI considerations.