FPGA Design and Timing Modeling Engineer

Quick Facts

• Role: Senior FPGA Design & Timing Modeling Engineer

Description

As a Senior FPGA Design & Timing Modeling Engineer, you translate FPGA circuit behavior and performance into accurate timing models used by Vivado to compile, analyze, and optimize customer designs. You develop methodologies and automation flows to improve timing accuracy, investigate mismatches between simulated/model predictions and measured silicon performance, and reduce unnecessary design margins. You collaborate across front-end design, circuit design, custom layout, place and route, and device modeling/capture teams to enable successful Vivado timing release for programmable devices.

Responsibilities

• Generate simulation-based delays using existing hardware designs to match FPGA timing arcs per the device model
• Develop automation flows to improve FPGA timing quality
• Drive silicon-based characterization of FPGA resources and root-cause mis-correlation with the expected timing model
• Perform performance analysis on complex designs using Vivado
• Coordinate release readiness reviews and manage risk mitigation plans
• Train junior team members and deliver time-sensitive results with quality

Requirements

• Strong understanding of digital circuits and FPGA device architecture
• Experience in timing analysis, simulation, silicon characterization, and engineering automation
• Experience investigating differences between simulated/model predictions and measured silicon performance

Benefits

AMD benefits at a glance.