IP Integration Engineer

Quick Facts

• Role: IP Integration Engineer (Remote, USA)
• Experience: 7+ years (or 5–7 years with a 4-year degree; or 3 years with an advanced degree; or equivalent)

Description

Lead subsystem/SoC IP integration for 1P and 3P IPs, including 3P fabric generation, quality checks, and PD handoff. Use RTL/digital expertise and Verilog/SystemVerilog to deliver synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure (CDC, Lint, RDC, register integration). Provide clear customer progress updates and solve complex integration problems independently.

Responsibilities

• Understand RTL design and digital concepts to support integration activities
• Perform subsystem or SoC integration
• Integrate 1P and 3P IPs, including generating 3P fabrics, quality checks, and PD handoff
• Execute SS integration using Verilog/SystemVerilog
• Apply synthesis and timing constraints, incorporate floor-planning considerations, and optimize performance
• Drive design-quality closure: CDC, Lint, RDC, and register integration
• Report daily/weekly customer progress
• Ensure customer satisfaction
• Contribute to process improvements and support colleagues

Requirements

• 7+ years of relevant experience (or 5–7 years with a 4-year degree; or 3 years with an advanced degree; or equivalent)
• In-depth RTL design and digital concepts knowledge
• Experience integrating subsystems or SoCs and integrating 1P/3P IPs
• Experience with quality checks and PD handoff
• Strong skills in Verilog/SystemVerilog, synthesis, timing constraints, and floor-planning/performance optimization
• Experience with design-quality closure including CDC, Lint, RDC, and register integration
• Ability to work independently, solve complex problems, and provide informal guidance to junior staff

Benefits

Opportunity to independently lead complex IP integration work and grow/stabilize long-term in the role.